Twin-Channel (TC)-MOSFET with twin omega-gate (Ω-gate) Si channels and its fabrication process were proposed. The twin Si channels are able to be fabricated by self-aligned process utilizing wet etching of SiN and silicon-on-insulator (SOI) wafers. Three-dimensional (3-D) device simulation was performed to optimize gate structure for TC-MOSFET with 10 nm10 nm (TSiWG) channels with the gate length of 30 nm, and it was found that TC-MOSFET with right-angled Ω-gate in case the Lunder was 3 nm showed excellent device characteristics similar to the gate-all-around (GAA) devices corresponding to the gate structure as Lunder=5 nm. Fabrication process of twin Si channels was also investigated experimentally, and approximately 40 nm40 nm twin Si channels were successfully fabricated on SOI by the proposed fabrication process.

Ferroelectric gate field-effect transistors (MFSFETs) were investigated utilizing nondoped HfO2 deposited by RF magnetron sputtering utilizing Hf target. After the post-metallization annealing (PMA) process with Pt top gate at 500°C/30s, ferroelectric characteristic of 10nm thick nondoped HfO2 was obtained. The fabricated MFSFETs showed the memory window of 1.7V when the voltage sweep range was from -3 to 3V.

In this paper, the effects of the TiN encapsulating layer and the dopant segregation process on the interface properties and the Schottky barrier height reduction of PdEr-silicide/n-Si(100) were investigated. The results show that controlling the initial location of the boron dopants by adding the TiN encapsulating layer lowered the Schottky barrier height (SBH) for hole to 0.20 eV. Furthermore, the density of interface states (Dit) on the order of 1011eV-1cm-2 was obtained indicating that the dopant segregation process with TiN encapsulating layer effectively annihilated the interface states.

We have investigated the in-situ N2-plasma nitridation for high-k HfN gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering to improve the electrical characteristics. It was found that the increase of nitridation gas pressure for the deposited HfN1.1 gate insulator, such as 98 mPa, decreased both the hysteresis width in C-V characteristics and leakage current. Furthermore, the 2-step nitiridation process with the nitridation gas pressure of 26 mPa followed by the nitridation at 98 mPa realized the decrease of equivalent oxide thickness (EOT) to 0.9 nm with decreasing the hysteresis width and leakage current. The fabricated metal-insulator-semiconductor field-effect transistor (MISFET) with 2-step nitridation showed a steep subthreshold swing of 87 mV/dec.

We investigated the low temperature formation of Pd2Si on Si(100) with TiN encapsulating layer formed at 500°C/1 min. Furthermore, the dopant segregation process was performed with ion dose of 1x1015 cm-2 for B+. The uniform Pd2Si was successfully formed with low sheet resistance of 10.4 Ω/sq. Meanwhile, the PtSi formed on Si(100) showed rough surface morphology if the silicidation temperature was 500°C. The estimated Schottky barrier height to hole of 0.20 eV (qφBp) was realized for n-Si(100).

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon should be realized. In this paper, flattening process of Si surface below 1000 utilizing Ar/4.9%H2 annealing and its effect on ultrathin HfON gate insulator formation were investigated. The Si(100) substrates were annealed using conventional rapid thermal annealing (RTA) system in Ar or Ar/4.9%H2 ambient for 1 h. The surface roughness of Ar/4.9%H2-annealed Si was small compared to that of Ar-annealed Si because the surface oxidation was suppressed. The obtained root mean square (RMS) roughness was 0.08 nm (as-cleaned: 0.20 nm) in case of Ar/4.9%H2-annealed at 1000 measured by tapping mode atomic force microscopy (AFM). The HfON surface was also able to be flattened by reduction of Si surface roughness. The electrical properties of HfON gate insulator were improved by the reduction of Si surface roughness. We obtained equivalent oxide thickness (EOT) of 0.79 nm (as-cleaned: 1.04 nm) and leakage current density of 3.510-3 A/cm2 (as-cleaned: 6.110 -1 A/cm2) by reducing the Si surface roughness.

In this research, we investigated the effect of Hf inter layer and chemical oxide on Si(100) substrate on the ferroelectric undoped HfO2 deposition. In case with 1 nm-thick Hf inter layer, equivalent oxide thickness (EOT) was decreased from 6.0 to 4.8 nm for 10 nm-thick HfO2 with decreasing annealing temperature. In case with 0.5 nm-thick chemical oxide, EOT was decreased from 3.9 to 3.6 nm in MFS diodes for 5 nm-thick HfO2. The MFSFET was fabricated with 10 nm-thick HfO2 utilizing Hf inter layer. The subthreshold swing was improved from 240 mV/dec. to 120 mV/dec. and saturation mobility was increased from 70 cm2/(Vs) to 140 cm2/(Vs) by inserting Hf inter layer.

In this research, the effect of Ar/N2-plasma sputtering gas pressure on the LaBxNy tunnel and block layer was investigated for pentacene-based floating-gate memory with an amorphous rubrene (α-rubrene) passivation layer. The influence of α-rubrene passivation layer for memory characteristic was examined. The pentacene-based metal/insulator/metal/insulator/semiconductor (MIMIS) diode and organic field-effect transistor (OFET) were fabricated utilizing N-doped LaB6 metal layer and LaBxNy insulator with α-rubrene passivation layer at annealing temperature of 200°C. In the case of MIMIS diode, the leakage current density and the equivalent oxide thickness (EOT) were decreased from 1.2×10-2 A/cm2 to 1.1×10-7 A/cm2 and 3.5 nm to 3.1 nm, respectively, by decreasing the sputtering gas pressure from 0.47 Pa to 0.19 Pa. In the case of floating-gate type OFET with α-rubrene passivation layer, the larger memory window of 0.68 V was obtained with saturation mobility of 2.2×10-2 cm2/(V·s) and subthreshold swing of 199 mV/dec compared to the device without α-rubrene passivation layer.

HfOxNy thin films formed by the electron cyclotron resonance (ECR) Ar/N2 plasma nitridation of HfO2 films were investigated for high-k gate insulator applications. HfOxNy thin films formed by the ECR Ar/N2 plasma nitridation (60 s) of 1.5-nm-thick HfO2 films, which were deposited on chemically oxidized Si(100) substrates, were found to be effective for suppressing interfacial layer growth or crystallization during postdeposition annealing (PDA) in N2 ambient. After 900 PDA of for 5 min in N2 ambient, it was found that HfSiON film with a relatively high dielectric constant was formed on the HfOxNy/Si interface by Si diffusion. An equivalent oxide thickness (EOT) of 2.0 nm and a leakage current density of 1.010-3 A/cm2 (at VFB-1 V) were obtained. The effective mobility of the fabricated p-channel metal-insulator-semiconductor field-effect transistor (MISFET) with the HfOxNy gate insulator was 50 cm2/Vs, and the gate leakage current of the MISFET with the HfOxNy gate insulator was found to be well suppressed compared with the MISFET with the HfO2 gate insulator after 900 PDA because of the nitridation of HfO2.

Pentacene-based organic field-effect transistors (OFETs) with SiO2 and HfON gate insulators have been fabricated, and the effect of gate insulator on the electrical properties of pentacene-based OFETs and the microstructures of pentacene films were investigated. It was found that the grain size for pentacene film deposited on HfON gate insulator is larger than that for pentacene film deposited on SiO2 gate insulator. Due to the larger grain size, pentacene-based OFET with HfON gate insulator shows better electrical properties compared to pentacene-based OFET with SiO2 gate insulator. Meanwhile, low-temperature (such as 140) fabricated pentacene-based OFET with HfON gate insulator was also investigated. The OFET fabricated at 140 shows a small subthreshold swing of 0.14 V/decade, a large on/off current ratio of 4 104, a threshold voltage of -0.65 V, and a hole mobility of 0.33 cm2/Vs at an operating voltage of -2 V.

For the further scaling and lower voltage applications of nonvolatile ferroelectric memory, the effect of Kr/O2 sputtering for SrBi2Ta2O9 (SBT) thin film formation was investigated utilizing a SrBi2Ta2O9 target. The 80-nm-thick SBT films were deposited by radio-frequency (RF) magnetron sputtering on Pt/Ti/SiO2/Si(100). Compared with Ar/O2 sputtering, the ferroelectric properties such as larger remnant polarization (Pr) of 3.2 μC/cm2 were observed with decrease of leakage current in case of Kr/O2 sputtering. X-ray diffraction (XRD) patterns indicated that improvement of the crystallinity with suppressing pyrochlore phases and enhancing ferroelectric phases was realized by Kr/O2 sputtering.

In this research, we investigated the threshold voltage (VTH) control by partial polarization of metal-ferroelectric-semiconductor field-effect transistors (MFSFETs) with 5 nm-thick nondoped HfO2 gate insulator utilizing Kr-plasma sputtering for Pt gate electrode deposition. The remnant polarization (2Pr) of 7.2 μC/cm2 was realized by Kr-plasma sputtering for Pt gate electrode deposition. The memory window (MW) of 0.58 V was realized by the pulse amplitude and width of -5/5 V, 100 ms. Furthermore, the VTH of MFSFET was controllable by program/erase (P/E) input pulse even with the pulse width below 100 ns which may be caused by the reduction of leakage current with decreasing plasma damage.

In this paper, the influence of high-temperature sputtering on the nitrogen-doped (N-doped) LaB6 thin film formation utilizing RF sputtering was investigated. The N-doped LaB6/SiO2/p-Si(100) MOS diode and N-doped LaB6/p-Si(100) of Schottky diode were fabricated. A 30 nm thick N-doped LaB6 thin film was deposited from room temperature (RT) to 150°C. It was found that the resistivity was decreased from 1.5 mΩcm to 0.8 mΩcm by increasing deposition temperature from RT to 150°C. The variation of work function was significantly decreased in case that N-doped LaB6 thin film deposited at 150°C. Furthermore, Schottky characteristic was observed by increasing deposition temperature to 150°C. In addition, the crystallinity of N-doped LaB6 thin film was improved by increasing deposition temperature.

We have investigated post-metallization annealing (PMA) utilizing TiN gate electrode on the thin ferroelectric undoped HfO2 directly deposited on p-Si(100) by RF magnetron sputtering. By post-deposition annealing (PDA) process at 600°C/30 s in N2, the memory window (MW) in the C-V characteristics was observed in the Al/HfO2/p-Si(100) diodes with 15 to 24-nm-thick HfO2. However, it was not obtained when the thickness of HfO2 was 10 nm. On the other hand, the MW was observed for Pt/TiN/HfO2 (10 nm)/p-Si(100) diodes utilizing PMA process at 600°C/30 s. The MW was 0.5 V when the bias voltage was applied from -3 to 3 V.

In this paper, the effect of a nitrogen-doped (N-doped) LaB6 interfacial layer (IL) on p-type pentacene-based OFET was investigated. The pentacene-based OFET with top-contact/back-gate geometry was fabricated. A 2-nm-thick N-doped LaB6 interfacial layer deposited on an 8-nm-thick SiO2 gate insulator. A 10-nm-thick pentacene film was deposited by thermal evaporation at 100°C followed by Au contact and Al back gate electrodes formation. The fabricated OFET showed normally- off characteristics and a steep subthreshold swing (SS) of 84 mV/dec. from ID-VG and ID-VD characteristics. Furthermore, the aging characteristics of 6 months after the fabrication were investigated and it was found that VTH and SS were stable when the N-doped LaB6 IL was introduced at the interface between SiO2 gate insulator and pentacene.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

The AuGe-alloy source and drain (S/D) formed on SiO2/Si(100) by the lithography process was investigated for the scaling of the organic field-effect transistors (OFETs) with bottom-contact geometry. The S/D was fabricated by the lift-off process utilizing the resist of OFPR. The OFETs with minimum channel length of 2.4 µm was successfully fabricated by the lift-off process. The fabrication yield of Au S/D was 57%, while it was increased to 93% and 100% in case of the Au-1%Ge and Au-7.4%Ge S/D, respectively. Although the mobility of the OFETs with Au-7.4%Ge S/D was decreased to 1.1×10-3 cm2/(Vs), it was able to be increased to 5.5×10-2 cm2/(Vs) by the surface cleaning utilizing H2SO4/H2O2 mixture solution (SPM) and post metallization annealing (PMA) after lift-off process, which was higher than that of OFET with Au S/D.

In this research, we investigated the digital/analog-operation utilizing ferroelectric nondoped HfO2 (FeND-HfO2) as a blocking layer (BL) in the Hf-based metal/oxide/nitride/oxide/Si (MONOS) nonvolatile memory (NVM), so called FeNOS NVM. The Al/HfN0.5/HfN1.1/HfO2/p-Si(100) FeNOS diodes realized small equivalent oxide thickness (EOT) of 4.5 nm with the density of interface states (Dit) of 5.3 × 1010 eV-1cm-2 which were suitable for high-speed and low-voltage operation. The flat-band voltage (VFB) was well controlled as 80-100 mV with the input pulses of ±3 V/100 ms controlled by the partial polarization of FeND-HfO2 BL at each 2-bit state operated by the charge injection with the input pulses of +8 V/1-100 ms.